Of bits and chips

VLSI Design

VLSI Design automation is characterized by a number of interesting combinatorial optimization problems, the primary ones being Partitioning, , Placement and Routing . My research is concerned with the development of strategies, for the identification of combinatorial structures satisfying certain pre-specified properties. Partitioning problems involve the splitting of a network into two or more parts to satisfy physical requirements, while placement problems involve computing the exact position on the chip of a particular component. Routing completes the chip design effort, by connecting up the individual components as dictated by the logical function of the chip.

Design Automation problems are notoriously hard and one of the challenges is to design efficient algorithms that solve these problems approximately.

Publications

Journals
Refereed Conferences
Miscellaneous
1. On the Complexity of a Partitioning problem in VLSI Design
  M.S. Thesis, University of Maryland, College Park, May 2000.
2. On the Combinatorics of Point Placement
  Technical Report, Cadence Design Systems, June 1996.
3. Improved algorithms for Point Placement
  Technical Report, Cadence Design Systems, June 1996.
4. Fast algorithms for PCB Placement
  Technical Report, Cadence Design Systems, June 1995.

Publications

Journals

Refereed Conferences

Miscellaneous