Schedule
| Date | Subject and Associated Reading |
Projects | Homework |
|---|---|---|---|
| 1/7 | Class Policies Introduction to Analog IC Design (3.1-3.2) Semiconductor Overview |
||
| 1/14 |
Transport of Charged Particles p-n Junctions (1.1-1.2) Bipolar Junction Transistors (1.3.1) MOS Capacitors |
HW 1 Due | |
| 1/21 |
Video Lectures (No Class) MOS Transistor Operation (1.5) Subthreshold MOSFET Modeling (1.8.1) |
P01 Due | HW 2 Due |
| 1/28 |
Subthreshold MOSFET Modeling (1.8.1) Channel-Length Modulation (1.5) Above-Threshold MOSFET Modeling (1.5) |
||
| 2/4 |
Backgate/Body Effect (1.6.6) Single-Transistor Circuits Basic Current Mirrors (4.1, 4.2.1, 4.2.2.2) Introduction to Single-Stage Amplifiers (3.1-3.2) Small-Signal Modeling (1.6.1-1.6.6) |
P02 Due |
HW 3 Due |
| 2/11 |
Simulation
Models Common-Source Amplifier (3.3.2, 4.3.1-4.3.4) |
P03 Due |
|
| 2/18 |
Test 1 Source Follower (3.3.7) |
P04 Due |
|
| 2/25 |
Common-Gate Amplifier (3.3.4-3.3.5) Source Degeneration (3.3.9) |
HW 4 Due |
|
| 3/4 |
Cascoded Gain Stages (3.4.2-3.4.4) Advanced Current Mirror Design (4.2.4-4.2.6) |
P05 Due |
|
| 3/11 |
Spring Break (No Class) |
||
| 3/18 |
Parasitic Capacitances (1.6.7-1.6.8) Time and Frequency Responses of Circuits (7.1-7.2.1, 7.3) |
||
| 3/25 |
Miller Theorem (7.1-7.2.1, 7.3) Physical Layout of CMOS Integrated Circuits (2.8-2.10) Differential Pairs (3.5) |
P06 Due |
HW 5 Due |
| 4/1 |
Differential Pairs (3.5) |
P07 Due |
|
| 4/8 |
Operational Transconductance Amplifiers One-Stage Operational Amplifiers (6.2, 6.5-6.7) Layout and Mismatch Considerations (2.8-2.10) |
HW 6 Due |
|
| 4/15 |
Test 2 High-Gain Opamps (6.4-6.7) |
P08 Due |
|
| 4/22 |
High-Gain
Opamps (6.4-6.7) Feedback and Compensation within Opamps (6.4-6.7) Short-Channel Effects (1.7) |
||
| 4/29 |
Final Project Presentations |